Drain and/or gate interconnect and finger structure
US11424333B2 · kind B2 · utility
3Cited by
33References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2020 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Aug 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.