Adaptive clock duty-cycle controller
US11424736B1 · kind B1 · utility
6Cited by
8References
31Claims
0Family size
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Key dates
| Filing date | Sep 25, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | Sep 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.