Enabling devices with enhanced persistent memory region access
US11429544B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jan 27, 2021 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Feb 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.