Implementing a hardware description language memory using heterogeneous memory primitives
US11429769B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2020 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Oct 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.