Patent · US Active

ESD protection in an electronic device

US11430749B2 · kind B2 · utility

0Cited by

4References

24Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Markus Mergens · Plainsboro, US
Werner Simbuerger · Haar, DE

Key dates

Filing date	Oct 24, 2019
Grant date	Aug 30, 2022
Priority date	—
Expiry date	May 13, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/911
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

According to one configuration, a fabricator produces an electronic device to include: a substrate; a transistor circuit disposed on the substrate; silicide material disposed on first regions of the transistor circuit; and the silicide material absent from second regions of the transistor circuit. Absence of the silicide material over the second regions of the respective of the transistor circuit increases a resistance of one or more parasitic paths (such as one or more parasitic transistors) in the transistor circuit. The increased resistance in the one or more parasitic paths provides better protection of the transistor circuit against electro-static discharge conditions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.