SRAM layout scheme for improving write margin
US11430796B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2020 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Mar 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor can apply different voltages to sources and bases (bulks, N-type well) of pull-up transistors and improves write margin of memory cells. An SRAM of the invention includes P-well regions PW_1 and PW_2, an N-well region NW, a first metal wire M1, and a second metal wire M2. The P-well regions PW_1 and PW_2 extend in a first direction, and pull-down transistors and accessing transistors are formed therein. The N-well region NW extends in first direction, and pull-up transistors are formed therein. The first metal wire M1 extends in the first direction on the N-well region NW and is electrically connected to the N-well region NW. The second metal wire M2 extends in a second direction orthogonal to the first direction and electrically connected to a common S/D region of a pair of pull-up transistors that are formed in the N-well region NW.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.