Method for fabricating semiconductor device
US11430878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Feb 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
A method includes etching a semiconductor substrate to form a plurality of semiconductor fins. The semiconductor fins are etched to form a recess. An epitaxy structure is grown in the recess. The epitaxy structure has a W-shape cross section. A capping layer is formed over the epitaxy structure. The capping layer is at least conformal to a sidewall of the epitaxy structure. The capping layer is etched to expose a top surface of the epitaxy structure. A first portion of the capping layer remains over the sidewall of the epitaxy structure after etching the capping layer. A contact is formed in contact with the exposed top surface of the epitaxy structure and the first portion of the capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.