Embedded ferroelectric memory cell
US11437084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2021 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Mar 4, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2275
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.