Chip structure and method for forming the same
US11437331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2019 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Dec 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13016
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.