Memory cell circuit, memory cell arrangement, and methods thereof
US11437402B2 · kind B2 · utility
3Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 7, 2021 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Apr 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.