Techniques for MRAM top electrode via connection
US11437433B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jul 16, 2020 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.