Patent · US Active

Structure and method for forming capacitors for a three-dimensional NAND

US11437464B2 · kind B2 · utility

1Cited by
0References
13Claims
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Inventors

Key dates

Filing dateDec 30, 2019
Grant dateSep 6, 2022
Priority date
Expiry dateJul 18, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2225/06548
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.