Virtualized caches
US11442856B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Dec 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.