Targeted very long delay for increasing speculative execution progression
US11443044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2019 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Jan 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for advancing speculative execution in microarchitectures is disclosed. A non-limiting example of the computer-implemented method includes receiving, by a processor, a test scenario including a first load instruction from a first memory location flagged with a delay notification and a speculative memory access instruction from a second memory following the first load instruction. The method executes, by the processor, the first load instruction from the first memory location and delays a return of data from the first memory location for a number of processor cycles. The method executes, by the processor, the speculative storage access instruction from the second memory location during the delay in returning the data from the first memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.