Subtractively patterned interconnect structures for integrated circuits

US11444024B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin Lin · Beaverton, US
• Noriyuki Sato · Hillsboro, US
• Tristan A. Tronic · Beaverton, US
• Michael Christenson · Beaverton, US
• Christopher J. Jezewski · Portland, US
• Jiun-Ruey Chen · Hillsboro, US
• James M. Blackwell · Portland, US
• Matthew V. Metz · Portland, US
• Miriam Reshotko · Portland, US
• Nafees Kabir · Portland, US
• Jeffery D. Bielefeld · Forest Grove, US
• Manish Chandhok · Beaverton, US
• Hui Jae Yoo · Hillsboro, US
• Elijah V. Karpov · Portland, US
• Carl Naylor · Portland, US
• Ramanan V. Chebiam · Hillsboro, US

Key dates

• Filing date: Nov 2, 2020
• Grant date: Sep 13, 2022
• Expiry date: Nov 2, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2221/1078
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.