Process of realization of an area of individualization of an integrated circuit
US11444041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Mar 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing an individualisation area includes providing at least a first level of the electrical tracks. The method includes depositing a dielectric layer and a deformable layer on the interconnection level. The method includes producing, in an area of the deformable layer, recessed patterns, by penetrating an imprint mould into the deformable layer, the production of the patterns being configured so that the patterns have a randomness in the deformable layer, thus forming random patterns. The method includes transferring the random patterns into the dielectric layer to form transferred random patterns therein and exposing the vias located in line with the transferred random patterns. The method includes filling the transferred random patterns with an electrically conductive material so as to form electrical connections between vias. The method includes producing a second level of the electrical tracks on the vias and the electrical connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.