Semiconductor package including a package substrate including staggered bond fingers
US11444052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Sep 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate including: first and second bond finger arrays, each of the first and second finger arrays arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bond finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bond finger array; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.