Integrated circuit structure with avalanche junction to doped semiconductor over semiconductor well
US11444076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Feb 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.