Channel structure having tunneling layer with adjusted nitrogen weight percent and methods for forming the same
US11444163B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Apr 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of memory devices and fabrication methods thereof are disclosed. In an example, a memory device includes a substrate, a memory stack, and a channel structure. The memory stack includes interleaved conductor layers and dielectric layers over the substrate. The channel structure extends through the memory stack into the substrate and includes a functional layer that includes a tunneling layer of which a nitrogen weight percent is not greater than about 28%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.