Isolation structures in multi-gate semiconductor devices and methods of fabricating the same
US11444179B2 · kind B2 · utility
3Cited by
1References
20Claims
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Key dates
| Filing date | Nov 20, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a semiconductor substrate, an oxide layer disposed over the semiconductor substrate, a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers, and an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.