Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures
US11445616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2018 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Jan 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.