Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit
US11449347B1 · kind B1 · utility
3Cited by
41References
18Claims
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Key dates
| Filing date | May 23, 2019 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.