Method to perform secondary-PG aware buffering in IC design flow
US11449660B1 · kind B1 · utility
1Cited by
15References
20Claims
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Key dates
| Filing date | Mar 10, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Mar 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.