Dividing circuit system and semiconductor memory system including thereof
US11450366B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | May 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.