Shared decoder circuit and method
US11450367B2 · kind B2 · utility
0Cited by
30References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 23, 2021 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Feb 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a selection circuit configured to receive a first address from a first port and a second address from a second port, a first latch circuit coupled to the selection circuit and configured to output each of the first address and the second address received from the selection circuit, a decoder, and a control circuit. The control circuit is configured to generate a plurality of signals configured to cause the decoder to decode each of the first address and the second address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.