Packaging process for side-wall plating with a conductive film
US11450534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Feb 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.