Structure with different stress-inducing isolation dielectrics for different polarity FETs
US11450573B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.