Warpage control of semiconductor die
US11450584B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Aug 19, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Aug 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.