Coupling of integrated circuits (ICS) through a passivation-defined contact pad
US11450630B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Oct 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19104
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.