Patent · US Active

Bonded three-dimensional memory devices having bonding layers

US11450653B2 · kind B2 · utility

2Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 10, 2020
Grant dateSep 20, 2022
Priority date
Expiry dateJun 5, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/14511
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.