Partially silicided nonvolatile memory devices and integration schemes

US11450677B2 · kind B2 · utility

Assignee

• GlobalFoundries Singapore Pte. Ltd. · SG

Inventors

• Lanxiang Wang · Singapore, SG
• Shyue Seng Tan · Singapore, SG
• Xinshu Cai · Singapore, SG
• Eng Huat Toh · Singapore, SG
• Yongshun Sun · Singapore, SG

Key dates

• Filing date: Nov 9, 2020
• Grant date: Sep 20, 2022
• Expiry date: Apr 10, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/683

Abstract

A nonvolatile memory device may be provided. The nonvolatile memory device comprises an active region, an n-well region and an isolation region separating the active region and the n-well region. A floating gate may be provided. The floating gate may be arranged over a portion of the active region and over a first portion of the n-well region. A first doped region in the active region may be laterally displaced from the floating gate on a first side and a second doped region in the active region may be laterally displaced from the floating gate on a second side opposite to the first side. A contact may be arranged over the n-well region, whereby the contact may be laterally displaced from a first corner of the floating gate over the first portion of the n-well region. A silicide exclusion layer may be arranged at least partially over the floating gate.