Patent · US Active

Integrated circuit with double isolation of deep and shallow trench-isolation type

US11450689B2 · kind B2 · utility

0Cited by

3References

11Claims

0Family size

Assignee

STMicroelectronics SA

Inventors

Thomas Bedecarrats · Grenoble, FR
Philippe Galy · Meylan, FR

Key dates

Filing date	Jul 13, 2020
Grant date	Sep 20, 2022
Priority date	—
Expiry date	Jul 13, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76229
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.