Carrier and component with a buffer layer, and method for producing a component
US11450794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2018 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Nov 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0364
Abstract
A carrier and a component are disclosed. In an embodiment a component includes a semiconductor chip including a substrate and a semiconductor body arranged thereon and a metallic carrier having a coefficient of thermal expansion which is at least 1.5 times greater than a coefficient of thermal expansion of the substrate or of the semiconductor chip, wherein the semiconductor chip is attached to a mounting surface of the metallic carrier by a connection layer such that the connection layer is located between the semiconductor chip and a buffer layer and adjoins a rear side of the semiconductor chip, wherein the buffer layer has a yield stress which is at least 10 MPa and at most 300 MPa, and wherein the substrate of the semiconductor chip and the metallic carrier of the component have a higher yield stress than the buffer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.