Managing sequential write performance consistency for memory devices
US11455107B2 · kind B2 · utility
1Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Oct 28, 2019 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Oct 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is implemented for a memory sub-system that detects a sequential write pattern in a write sequence for a memory device in a set of commands received from a host, detects current bandwidth utilization deviating from a write bandwidth utilization performance target, in response to detecting the sequential write pattern, and adjusts write bandwidth utilization to conform to the write bandwidth utilization target, in response to detecting the current bandwidth utilization deviating from the write bandwidth utilization performance target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.