Memory system and operating method thereof
US11455120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Nov 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system may include: a memory device comprising a plurality of channels, a plurality of dies coupled to the respective channels, and a plurality of super blocks; and a controller suitable for controlling the memory device, wherein the controller includes: a detector suitable for searching for a first available reserved block in a first die, when a bad block has occurred in the first die which is coupled to a first channel and belongs to a first super block group, and searching for a second available reserved block in a second die which is coupled to the first channel and belongs to a second super block group when the first available reserved block is not present in the first die; and an assignor suitable for replacing the bad block with the second available reserved block when the second available reserved block is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.