Using flag qubits for fault-tolerant implementations of topological codes with reduced frequency collisions
US11455207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2019 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Aug 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of error correction for a quantum computer includes identifying each of a plurality of physical qubits arranged in a lattice pattern over a surface in a quantum processor of the quantum computer as a one of a data qubit, an ancilla qubit or a flag qubit to define a plurality of data qubits, ancilla qubits and flag qubits. Each pair of interacting data qubits interact with a flag qubit and adjacent flag qubits both interact with a common ancilla qubit. The method further includes performing measurements of weight-four stabilizers, weight-two stabilizers, or both of a surface code formed using at least a sub-plurality of the plurality of physical qubits, or performing measurements of weight-four Bacon-Shor type gauge operators; and correcting fault-tolerantly quantum errors in one or more of the at least sub-plurality of physical qubits based on a measurement from at least one flag qubit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.