Christopher Chamberland
25Patents
3h-index
29Co-inventors
55Inventor score
Filing activity: May 22, 2018 → Jan 13, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11321627B1 | Fault-tolerant quantum hardware using hybrid acoustic-electrical qubits | Electricity | 11 | Active |
| US10972133B2 | Flag fault-tolerant error correction with arbitrary distance codes | Electricity | 8 | Active |
| US11455207B2 | Using flag qubits for fault-tolerant implementations of topological codes with reduced frequency collisions | Physics | 6 | Active |
| US11580436B2 | Stabilizer measurement decoding using additional edges to identify errors caused by cross-talk | Electricity | 3 | Active |
| US11556411B2 | Quantum code for reduced frequency collisions in qubit lattices | Electricity | 3 | Active |
| US11468219B2 | Toffoli gate preparation for a quantum hardware system comprising hybrid acoustic-electrical qubits | Physics | 3 | Active |
| US11741279B2 | Toffoli gate distillation from Toffoli magic states | Electricity | 2 | Active |
| US11966817B1 | Teleporting magic states from a color code to a surface code and decoding a merged surface-color code | Physics | 2 | Active |
| US11900221B1 | Error correction decoding techniques for lattice surgery | Physics | 2 | Active |
| US12007835B1 | Temporally encoded lattice surgery protocols for hybrid error detection and correction schemes | Physics | 1 | Active |
| US11853159B1 | Edge graph mapping using analog information with dynamically updated weighting factors for a surface GKP code | Physics | 1 | Active |
| US11599820B1 | Fault-tolerant quantum error correction with a surface GKP code | Physics | 1 | Active |
| US12093785B2 | High-fidelity measurement of bosonic modes | Physics | 1 | Active |
| US11645570B1 | Preparation of qunaught states for a surface GKP code using a three (or higher) level ancilla system | Physics | 0 | Active |
| US12008438B1 | Lattice surgery techniques using twists | Physics | 0 | Active |
| US12057859B1 | Treating circuit-level noise using a local and global decoding scheme | Electricity | 0 | Active |
| US12423606B1 | Quantum codes implemented using cat data qubits and transmon ancilla qubits | Physics | 0 | Active |
| US12165006B1 | Lattice surgery techniques without using twists | Physics | 0 | Active |
| US11983601B2 | Hybrid bacon-shor surface codes in a concatenated cat-qubit architecture | Electricity | 0 | Active |
| US12165013B1 | Training neural network local decoders for circuit-level quantum error correction | Electricity | 0 | Active |
| US12373726B1 | Quantum computer designs with core computing and cache regions that utilize lattice surgery | Physics | 0 | Active |
| US12093789B2 | Quantum code for reduced frequency collisions in qubit lattices | Electricity | 0 | Active |
| US11941483B2 | Cross-talk reduction in fault tolerant quantum computing system | Electricity | 0 | Active |
| US12169673B2 | Toffoli gate preparation for a quantum hardware system comprising hybrid acoustic-electrical qubits | Physics | 0 | Active |
| US11449783B2 | Trivalent lattice scheme to identify flag qubit outcomes | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.