Verifying a hardware design for a component that implements a permutation respecting function
US11455451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2019 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | May 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.