Silicon-on-insulator wafer and low temperature method to make thereof

US11456204B1 · kind B1 · utility

Inventor

• Alexander Usenko · New Providence, US

Key dates

• Filing date: Apr 4, 2021
• Grant date: Sep 27, 2022
• Expiry date: Apr 4, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02667
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance. Process uses only standard equipment readily available at semiconductor foundries; therefore, the process can be easily implemented at foundries.