Alexander Usenko
17Patents
10h-index
8Co-inventors
65Inventor score
Filing activity: Feb 2, 2000 → Sep 15, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6806171B1 | Method of producing a thin layer of crystalline material | Emerging Cross-Sectional Technologies | 277 | Expired |
| US6352909B1 | Process for lift-off of a layer from a substrate | Electricity | 99 | Expired |
| US6368938B1 | Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate | Electricity | 81 | Expired |
| US6387829B1 | Separation process for silicon-on-insulator wafer fabrication | Emerging Cross-Sectional Technologies | 69 | Expired |
| US6346459B1 | Process for lift off and transfer of semiconductor devices onto an alien substrate | Electricity | 54 | Expired |
| US7148124B1 | Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers | Electricity | 53 | Expired |
| US6355493B1 | Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon | Electricity | 26 | Expired |
| US6344417B1 | Method for micro-mechanical structures | Performing Operations; Transporting | 24 | Expired |
| US6696352B1 | Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer | Performing Operations; Transporting | 22 | Expired |
| US6995075B1 | Process for forming a fragile layer inside of a single crystalline substrate | Electricity | 12 | Expired |
| US6861320B1 | Method of making starting material for chip fabrication comprising a buried silicon nitride layer | Electricity | 7 | Expired |
| US8796054B2 | Gallium nitride to silicon direct wafer bonding | Electricity | 0 | Active |
| US10921491B2 | Method of making a surface with improved mechanical and optical properties | Physics | 0 | Active |
| US12009252B2 | Method of making a silicon on insulator wafer | Electricity | 0 | Active |
| US12206030B2 | Stacked diode with side passivation and method of making the same | Electricity | 0 | Active |
| US8772875B2 | Semiconductor on glass substrate with stiffening layer | Electricity | 0 | Active |
| US11456204B1 | Silicon-on-insulator wafer and low temperature method to make thereof | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.