Semiconductor package
US11456241B2 · kind B2 · utility
1Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Oct 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.