Integrated circuit (IC) packages employing split, double-sided metallization structures to facilitate a semiconductor die (“die”) module employing stacked dice, and related fabrication methods
US11456291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Jun 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.