Microfluidic chips with one or more vias
US11458474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Mar 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N30/6095
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.