William Francis Landers
33Patents
9h-index
78Co-inventors
78Inventor score
Filing activity: Dec 6, 1995 → Sep 7, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5676587A | Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride | Electricity | 162 | Expired |
| US7098676B2 | Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor | Electricity | 38 | Expired |
| US6221775A | Combined chemical mechanical polishing and reactive ion etching process | Electricity | 28 | Expired |
| US6325696A | Piezo-actuated CMP carrier | Performing Operations; Transporting | 26 | Expired |
| US7312529B2 | Structure and method for producing multiple size interconnections | Emerging Cross-Sectional Technologies | 24 | Expired |
| US6650010B2 | Unique feature design enabling structural integrity for advanced low K semiconductor chips | Electricity | 22 | Expired |
| US5953115A | Method and apparatus for imaging surface topography of a wafer | Physics | 19 | Expired |
| US7544602B2 | Method and structure for ultra narrow crack stop for multilevel semiconductor device | Electricity | 15 | Active |
| US6296717A | Regeneration of chemical mechanical polishing pads in-situ | Electricity | 9 | Expired |
| US6815346B2 | Unique feature design enabling structural integrity for advanced low k semiconductor chips | Electricity | 8 | Expired |
| US7294565B2 | Method of fabricating a wire bond pad with Ni/Au metallization | Electricity | 8 | Expired |
| US7714452B2 | Structure and method for producing multiple size interconnections | Emerging Cross-Sectional Technologies | 8 | Active |
| US8546961B2 | Alignment marks to enable 3D integration | Electricity | 8 | Active |
| US7009280B2 | Low-k interlevel dielectric layer (ILD) | Electricity | 7 | Expired |
| US9059167B2 | Structure and method for making crack stop for 3D integrated circuits | Electricity | 7 | Active |
| US6102776A | Apparatus and method for controlling polishing of integrated circuit substrates | Performing Operations; Transporting | 7 | Expired |
| US7863183B2 | Method for fabricating last level copper-to-C4 connection with interfacial cap structure | Electricity | 6 | Active |
| US8691691B2 | TSV pillar as an interconnecting structure | Electricity | 6 | Active |
| US5897425A | Vertical polishing tool and method | Performing Operations; Transporting | 6 | Expired |
| US8859390B2 | Structure and method for making crack stop for 3D integrated circuits | Electricity | 5 | Active |
| US8386977B2 | Circuit design checking for three dimensional chip technology | Physics | 3 | Active |
| US11469485B2 | Embedded microstrip transmission line | Performing Operations; Transporting | 2 | Active |
| US8288270B2 | Enhanced electromigration resistance in TSV structure and design | Electricity | 2 | Active |
| US6048745A | Method for mapping scratches in an oxide film | Emerging Cross-Sectional Technologies | 2 | Expired |
| US11458474B2 | Microfluidic chips with one or more vias | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.