Memory device supporting a high-efficient input/output interface and a memory system including the memory device
US11461251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | May 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.