Junghwan Choi
81Patents
3h-index
108Co-inventors
65Inventor score
Filing activity: Jan 7, 2010 → Jul 15, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10255969B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 43 | Active |
| US8253455B2 | Delay locked loop circuit and operation method thereof | Electricity | 7 | Active |
| US9899075B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 4 | Active |
| US10062430B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 3 | Active |
| US11615833B2 | Multi-level signal receivers and memory systems including the same | Physics | 3 | Active |
| US11218343B2 | Memory device and memory system including the same | Emerging Cross-Sectional Technologies | 3 | Active |
| US9449653B2 | Memory chip package having optically and electrically connected chips, memory system having the same and driving method thereof | Electricity | 3 | Active |
| US11594267B2 | Memory device for receiving one clock signal as a multi-level signal and restoring original data encoded into the clock signal and method of operating the same | Emerging Cross-Sectional Technologies | 3 | Active |
| US11240676B2 | Analysis method and apparatus for distributed-processing-based network design in wireless communication system | Electricity | 2 | Active |
| US11587598B2 | Memory device for generating pulse amplitude modulation-based DQ signal and memory system including the same | Physics | 2 | Active |
| US11461251B2 | Memory device supporting a high-efficient input/output interface and a memory system including the memory device | Physics | 2 | Active |
| US11348623B2 | Memory device, controller controlling the same, memory system including the same, and operating method thereof | Electricity | 2 | Active |
| US11699472B2 | Semiconductor memory device and memory system including the same | Physics | 2 | Active |
| US11742016B2 | Quadrature error correction circuit and semiconductor memory device including the same | Electricity | 2 | Active |
| US12063044B2 | Digital phase locked loop and methods of operating same | Electricity | 2 | Active |
| US11627021B2 | Data processing device and memory system including the same | Emerging Cross-Sectional Technologies | 2 | Active |
| US11149033B2 | Heteroaryl compound, enantiomer, diastereomer or pharmaceutically acceptable salt thereof, and antiviral composition containing same as active ingredient | Chemistry; Metallurgy | 2 | Active |
| US11804838B2 | Transmitter circuit including selection circuit, and method of operating the selection circuit | Electricity | 1 | Active |
| US11581960B2 | Translation device, test system including the same, and memory system including the translation device | Electricity | 1 | Active |
| US12057156B2 | Quadrature error correction circuit and semiconductor memory device including the same | Electricity | 1 | Active |
| US11888654B2 | Offset detector circuit for differential signal generator, receiver, and method of compensating for offset of differential signal generator | Electricity | 1 | Active |
| US11789879B2 | Memory device supporting a high-efficient input/output interface and a memory system including the memory device | Physics | 1 | Active |
| US11657859B2 | Memory device, controller controlling the same, memory system including the same, and operating method thereof | Electricity | 1 | Active |
| US11824563B2 | Encoding and decoding apparatuses and methods for implementing multi-mode coding | Electricity | 1 | Active |
| US11791811B2 | Delay circuit and clock error correction device including the same | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.