Computation-in-memory in three-dimensional memory device
US11461266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2019 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Aug 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) memory devices are provided. An exemplary 3D memory device includes a 3D NAND memory array and an on-die data processing circuit coupled to the 3D NAND memory array on a same chip. The on-die data processing circuit is configured to receive, from an input/output (I/O) interface, control instructions for performing operations on data stored in the 3D NAND memory array. The on-die data processing circuit is also configured to retrieve the data from the 3D NAND memory array based on the control instructions and perform the operations on the retrieved data. Moreover, the on-die data processing circuit is configured to return a result of the operations to the I/O interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.