SDD ATPG using fault rules files, SDF and node slack for testing an IC chip
US11461520B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Feb 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.