Glitch analysis and glitch power estimation system
US11461523B1 · kind B1 · utility
3Cited by
0References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Feb 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.