System and method for reading and writing memory management data using a non-volatile cell based register
US11462249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Oct 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for reading and writing memory management data using a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.